Integrated circuits (IC) are single chips made of a semiconductor material with at least one interconnected array of active and passive elements capable of performing at least one complete electronic circuit function. In recent times the number of semiconductor devices formed on a chip such as transistors, diodes, and resistors has increased. With the increase of density of the integrated circuits it becomes necessary to shrink the dimensions of N-channel metal-oxide-semiconductor field-effect transistors (NMOS) and P-channel metal oxide semiconductor field effect transistors (PMOS).
The electrical operation of devices on semiconductor chips depends on regions of different doping types and concentrations. The electrical character of these regions is altered by introducing dopants into the substrate, accomplished by ion implantation and/or diffusion. Diffusion is the process by which a species moves as the result of the presence of a chemical gradient. The diffusion of controlled impurities or dopants into silicon is the basis of the P-N junction formation and device fabrication in very-large-scale integrated circuits (VLSI) processing.
In the earlier days of transistor and IC processing, dopants were supplied to the silicon by chemical sources. These dopants were then diffused to the desired depths by subjecting them to elevated temperatures (e.g., 900 to 1200 degrees Celsius). More recently, ion implantation has become a major means for the introduction of dopant atoms into silicon. Relatively shallow dopant profiles can be obtained by using low energy ion implantation. In addition, however, ion implanted devices are frequently subjected to elevated temperatures in order for the implanted impurities to become electrically active and so that defects from the implantation are removed by annealing. While the elevated temperatures electrically activate the dopant, the elevated temperatures may also cause diffusion of the dopants deeper into the silicon.
As the density of integrated circuits increases, it becomes necessary to shrink the dimensions of semiconductor devices such as NMOS and PMOS transistors. New problems and difficulties surface as the dimensions are reduced. One difficulty that has developed is producing transistors with the desired characteristics but with junction depths that accommodate the smaller dimensions. The junction depth affects all transistor dimensions because proper scaling between the junction depth and other important dimensions is typically required. For example, if junction depths are too great, the lateral extent of the junctions may short the device. Although shallower junctions may be desirable, it is also desirable to have certain performance characteristics met including reduced sheet resistivity and lower Miller capacitance.
Dopant species such as boron, which is frequently used for PMOSFET sources and drains, and phosphorus, which is often included in NMOSFET sources and drains, have high diffusion coefficients and rapidly diffuse into silicon. Furnace anneal temperatures in the 800 to 900.degree. C. range can be used to obtain the correct diffusion depth for boron and phosphorus for many sub-micron MOSFET designs. But, temperatures of 1000.degree. C. or higher are typically needed to fully activate these dopant species when they are present in the high concentrations desired for MOSFET sources and drains.
One approach to attempting to solve the difficulty of developing the desired performance without rendering the device inoperative is to increase the side spacer or sidewalls and then make a deeper junction. This approach, however, lessens the overlap so that there is less Miller capacitance, but the source potential barrier is lowered by the drain voltage, i.e., drain-induced barrier lowering (DIBL).
Another approach to attempting to address this difficulty would be to increase the total concentration of the dopant and activate the dopant with a lower annealing temperature; however, not all of the dopant would be activated. For example, if the annealing temperature being used will activate approximately half of the dopant, this approach would attempt to solve the problem of insufficiently activated dopant by doubling the total concentration. This approach is typically not satisfactory because the diffusion coefficient increases as total concentration increases. Thus, the decreased diffusion that would normally occur at lower annealing temperatures is offset by the increased diffusion caused by the higher diffusion coefficient that results from a greater total concentration.
Another approach attempting to solve the problem of obtaining good activation of the source and drain dopants would be to use RTP to both diffuse and activate these species. RTP is, however, very difficult to control and the maximum temperature will vary across a silicon wafer and can vary from wafer to wafer. This variation causes the depth and lateral extent of the source and drain to vary and decrease the yield of good integrated circuit chips.